INNOVATION

ECLA developed the first commercially available Content Inspection (CI) chip and licensed it to Raqia Networks in 2001.
The Raqia device, the ReGXP2G, has a look-aside architecture, operates at 2.4Gbps. and has a glue-less interface to NPUs.
The ReGXP2G product brief is here.
Please contact us at info@ecla.com on how to obtain devices, the complete data sheet or more information.

PRODUCTS

ECLA's CI Processor is optimized to perform at wire-speed Content Inspection and pattern matching for content signatures used in Deep Packet Inspection, Intrusion Detection and Prevention Systems and any other Layer 7 application and network security application. The CI Processor examines each byte of each packet at at 10Gbps wire rate. It is

The CI Processor operates at 10Gbps or 20Gbps, is fully customizable and is available for either a Xilinx Virtex 4 and 5 devices or an Altera Stratix 2 or 3 devices.

Features:

• Complete Deep Packet Inspection in an FPGA core.
• Deterministic performance.
• Full duplex operations up to 20Gbps.
• Inspects every byte of the packet, header as well payload, as well across packet boundaries.
• Optional on-chip database storage.
• Complete header checking, including checksum checking.
• Implements an EDFA (Efficient Finite Automata) based architecture. Each EFA combines a DFA Engine, a Hashing Engine and an optimizer for most efficient operation and database storage.
• Header check settings using dedicated registers or through regular expressions.
• Payload checking using regular expression signatures using our regular expression compiler.
• Supports a very large number of rules with DDR2, or DDR3 or RLDRAMII.
• Supports incremental rules update.
• Common API across all CI Processor family.
• Support for hundred of thousands signatures.
• Support for PERL compatible regular expressions.
• Availability of a rule compiler with incremental rule update support.
• Availability of a software simulator and a software emulator.
• Easy system integration.
• Customizable front end interface (PCI-Express, QDR, Ethernet or custom interface).
• Scalable performance.
• Look-aside operation with a customizable interface.
• Look-aside operation with a PCI-Express interface.
• In-line (bump in the wire) operation with a Ethernet or a SPI-4 Interface.

Look Aside System Integration with a Custom Interface

The block diagram shows a system block diagram with a customizable interface:

• 64 bit packet interface
• 64 bit results interface
• 32 bit system and configuration interface

The network Ethernet traffic is received by the Ethernet MAC or Switch and is directed to the NPU, who will then transfer the packets to be proccessed to the CI device.

Look Aside System Integration with a PCI-Express Interface

This implementation shows that all the traffic between the NPU and the CI uses the PCI-Express. This allows the integration of the CI FPGA and its associated memory on a separate PCI-E card.

In-Line System Integration with an Ethernet Interface

The block diagram shows a CI integrated in a system as an in-line device or bump in the wire. Traffic between the Ethernet device and the CI, can be either over an Ethernet 10Gbps link or over a SPI-4 interface. After completing CI and DPI processing, packets are forwarded by the CI to the NPU.

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